1Preface
765.7.1 Memory versus Processor Speed
2Chapter - 1 Introduction: Computer System Components
775.7.2 Machine Cycles
31.1 Computer System Organization
785.7.3 One-address Instructions
41.1.1 Hardware
795.7.4 Zero-Address Instructions
51.1.2 Software
805.7.5 Input/Output Instructions
61.2 Computer Evolution
815.8 Console
71.3 Design Vs. Architecture
825.9 Microprogrammed Control Unit: 5.9.1 MCU for ASC
81.4 Exercise
835.10 Excercise
9Chapter - 2 Combinational Logic
84Chapter - 6 Processor and System Structures
102.1 Basic Operations And Terminology
856.1 Types of Computer Systems
112.1.1 Evaluation of Expressions
866.2 Operand (Data) Types And Formats
122.1.2 Truth Tables
876.2.1 Decimal Data
132.1.3 Functions and Their Representation
886.2.2 Character Strings
142.1.4 Canonical Forms
896.2.3 Floating-point Numbers
152.1.5 Boolean Algebra (Switching Algebra)
906.2.4 IEEE Standard
162.1.6 Primitive Hardware Blocks
916.3 Instruction Set
172.1.7 Functional Analysis of Combinational Circuits
926.3.1 Instruction Length
182.1.8 Synthesis of Combinational Circuits
936.3.2 Opcode Selection
192.1.9 AND–OR Circuits
946.3.3 Addressing mode Opcode (H)
202.1.10 OR–AND Circuits
956.3.4 Instruction Formats
212.1.11 NAND–NAND and NOR–NOR Circuits
966.4 Registers
222.1.12 Some Popular Combinational Circuits
976.5 Addressing Modes
232.2 Exercise
986.5.1 Immediate Addressing
24Chapter - 3 Synchronous Sequential Circuits
996.5.2 Paged Addressing
253.2.1 FLIP-FLOPS
1006.5.3 Base-register Addressing
263.2.2 Analysis of Synchronous Sequential Circuits
1016.5.4 Relative Addressing
273.2.3 Design of Synchronous Sequential Circuits
1026.5.5 Implied (Implicit) Addressing
283.2.4 Registers
1036.6 Compaq Computer Corporation’s SP700 Workstation
293.2.5 Register Transfer Languages
1046.7 Alternative Workstation Architectures
303.2.6 Designing Sequential Circuits With Integrated Circuits
1056.7.1 A Crossbar Switch Architecture by Sun Microsystems – Ultra Port Architecture (UPA)
313.1 Exercise
1066.7.2 Unified Memory Architecture (UMA) by Silicon Graphics, Inc.
32Chapter - 4 A Simple Computer: Organization and Programming
1076.8 Exercise
334.1 A Simple Computer
108Chapter - 7 Memory System Enhancement
344.2 Data Format
1097.1 Speed Enhancement
354.3 Instruction Format
1107.1.1 Banking
364.4 Instruction Set
1117.1.2 Interleaving
374.5 Mnemonic
1127.1.3 Multiport Memories
384.5.1 Zero-Address Instructions
1137.1.4 Wider Word Fetch
394.5.2 One-address Instructions
1147.1.5 Instruction Buffer
404.5.3 Input/Output Instructions
1157.1.6 Cache Memory
414.6 Addressing Modes
1167.1.7 Address Translation
424.6.1 Direct Addressing
1177.1.8 Write Operations
434.6.2 Indexed Addressing
1187.1.9 Performance
444.6.3 Indirect Addressing
1197.2 Size Enhancement
454.6.4 Other Addressing Modes
1207.2.1 Page Size
464.7 Addressing Limitations
1217.2.2 Speed
474.8 Machine Language Programming
1227.2.3 Address Translation
484.9 ASC Assembler
1237.3 Address Extension
494.9.1 ORG Address Origin
1247.4 Example Systems
504.9.2 END Address Physical End
1257.4.1 Memory Management in Intel Processors
514.9.3 EQU- Equate
1267.4.2 Sun-3 System Memory Management
524.9.4 Example
1277.5 Exercise
534.9.5 BSS - Block Storage Starting
128Chapter - 8 Advanced Architectures
544.9.6 BSC - Block Storage of Constants
1298.1 Classes of Architectures
554.10 Assembly Process
1308.1.1 SIMD
564.11 Program Loading
1318.1.2 MISD
574.12 Exercise
1328.1.3 MIMD
58Chapter - 5 A Simple Computer: Hardware Design
1338.2 Example Systems
595.1 Program Execution
1348.2.1 Major Hardware Components
605.1.1 Instruction Fetch
1358.2.2 Hardware Organization and Physical Characteristics
615.1.2 Instruction Execution
1368.2.3 Cray T3E System
625.2 Data, Instruction, And Address Flow
1378.2.4 External Registers
635.2.1 Fetch phase
1388.2.5 Network Router
645.2.2 Address Calculations
1398.3 Processor Interconnection
655.2.3 Execution Phase
1408.4 I/O System
665.3 Bus Structure
1418.5 Operating System
675.4 Arithmetic And Logic Unit
1428.6 Software Support
685.4.1 ADD
1438.7 Server Function
695.4.2 COMP
1448.8 Performance Analysis Tools
705.4.3 SHR
1458.9 Data-flow Architectures
715.4.4 SHL
1468.10 Computer Networks And Distributed Processing
725.4.5 TRA1
1478.11 Excercise
735.5 Input/Output
148Glossary
745.6 Control Unit: 5.6.1 Types of Control Units
149Appendix
755.7 Hardwired Control Unit for ASC
150Index
