Pipelined RISC-V Computer Architecture
A Beginner-Friendly Guide to Logic Gates, Assembly Programming, and the Hardware Software InterfaceBy Tomasz Zielinski
Length16h 7m
About this audiobook
Start at a single logic gate and finish able to explain how a pipelined processor executes your C code.
This book never skips a layer. You build combinational blocks into an arithmetic logic unit, add flip-flops and timing constraints, design finite state machines, and model all of it in a hardware description language with testbenches. Then you meet the instruction set: register formats, encodings, assembly control flow, procedures and the stack, and the exact path from C source through compiler and linker to memory.
From there you construct a single-cycle datapath, pipeline it, resolve data and control hazards with forwarding and stalls, and measure the result. Caches, virtual memory, multicore parallelism and device input and output close the book. Every chapter connects the abstract model to the concrete hardware, so you always know which layer you are standing on and why the next one matters.
What you will learn:
• Convert between number systems and represent signed and unsigned values in binary
• Apply Boolean algebra to simplify expressions and build logic gates
• Combine gates into adders, multiplexers, decoders and other combinational blocks
• Use flip-flops, clocks and timing constraints to create reliable sequential logic
• Design finite state machines and implement them in a hardware description language with testbenches
• Read and write RISC-V assembly, including control flow, procedures and stack discipline
• Trace the path from C source through compiler and linker to machine code in memory
• Construct a single-cycle datapath and then pipeline it with forwarding and stalls
• Evaluate branch prediction, caches, virtual memory, parallelism and input-output
For computer engineering students and self-taught systems programmers who want a complete, hands-on path from digital logic to a working pipelined RISC-V processor. If you have basic programming experience and are ready to understand the hardware-software interface from the ground up, this book is for you.
Audiobook details
GenreTechnology
Length16 hrs 7 mins
Narrated byListen with 1,000+ voices
FormateBook with Audio
Publish dateSep 28, 2026
LanguageEnglish
Table of contents
1Pipelined RISC-V Computer Architecture
2Foreword
3Preface
4About This Book
5Chapter 1: Number Systems and Binary Representation
Show all chaptersShow less
61.1 Positional Notation and Base Conversion
71.2 Unsigned Binary Arithmetic and Range
81.3 Two’s Complement and Signed Arithmetic
91.4 Overflow Detection and Saturation
101.5 Fixed-Point and Floating-Point Formats
111.6 Precision, Rounding and Representation Limits
12Chapter 2: Boolean Algebra and Logic Gates
132.1 Logic Values, Gates and Truth Tables
142.2 Boolean Theorems and Algebraic Simplification
152.3 Canonical Forms and Standard Representations
162.4 Karnaugh Maps and Minimisation
172.5 Don’t-Care Conditions and Practical Minimisation
182.6 From Equations to Gate Networks
19Chapter 3: Combinational Building Blocks
203.1 Half Adders, Full Adders and Ripple Carry
213.2 Carry-Lookahead and Prefix Adders
223.3 Subtraction, Comparators and Condition Flags
233.4 Multiplexers, Decoders and Encoders
243.5 Shifters and Barrel Shifters
253.6 The Arithmetic Logic Unit
26Chapter 4: Sequential Logic
274.1 Latches, Flip-Flops and Level versus Edge Triggering
284.2 Registers, Register Files and Counters
294.3 Timing Analysis: Setup, Hold and Clock Skew
304.4 Metastability and Synchronizers
314.5 Reset Strategies and Clock Enables
32Chapter 5: Finite State Machines
335.1 State Diagrams, Moore and Mealy Models
345.2 State Encoding and State Assignment
355.3 Next-State and Output Logic Design
365.4 A Worked Controller: Traffic Light with Pedestrian Request
37Chapter 6: Hardware Description Languages
386.1 Modules, Ports and Structural Modelling
396.2 Behavioural and Dataflow Modelling
406.3 Parameterised Modules and Generate Constructs
416.4 Testbenches and Simulation
426.5 What Synthesis Produces and What It Rejects
43Chapter 7: The RISC-V Instruction Set
447.1 Registers, Program Counter and Instruction Categories
457.2 R, I, S, B, U and J Instruction Formats
467.3 Addressing Modes and Memory Access
477.4 Control Flow Instructions and Comparison
48Chapter 8: Assembly Programming
498.1 Arithmetic, Logic and Shift Instructions in Assembly
508.2 Branches, Loops and Conditional Execution
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